Notes on Alpha v Itanium
========================

Branch Delay slots.

Alpha was specially designed not to have branch delay slots;
i.e. spaces in the instruction stream where the compiler is figuring
out where the branch goes.  apparently on mips, around 20% of branch
delay slots are no-ops, becuase there isn't enough to do.

On Alpha 21064 they use branch prediction.  Initially the prediction
is set by the direction of the jump -- forward jumps predicted not
taken (if blah do blah) and backwards jumps predicted taken (while 1
do blah).  when branches are taken, prediction is based on which way
it went last time (prediction bits kept in i-cache)

what happens is that the processor takes what is in the target icache
and puts it in the pipeline.  later on the branch is resolved, the itb
figures out the correct physical address and the icache reports if it
was a hit or a miss.

Itanium obviously avoid this with the compiler scheduling
instructions.

In "The Alpha AXP Architecture and 21064 Processor" by Edward McLellan
(IEEE Micro, date?) he mentions that Alpha wanted to avoid contention
of having a single register/bit to give the result of comparisions
(condition codes), which causes contentions with branches.  Alpha
allowed the result in any register be the condition code for a branch.

Itanium has predicate registers (bits of a register) allowing 64
status bits, both negative and positive.